Micah Acinapura POCO Final 1. Interpertation is dynamic conversion of statements from one level to a lower one. As commands are passed to L1 they are converted into L0 instructions and then L1 passes them to L0. Translation is static conversion, all statements at one. Translation serves the same purpose as interpertation, converting instructions from one level to a lower one, however they are used for different purposes. Interpertation is faster and is used on the lower levels of the machine, where as translation is slower, because it has to convert all the instructions at one, and is usually used on the higher levels. 2. 0-Gates- Transistors form gates, gates form registers. 1-Mircoarch level- Register form a data path. Microcode controls data path. 2-Instruction Set Arch Level- Executes instructions recieved by OS. ISA instructions use multiple Micro instructions to perform a task. 3-Operating System level - Some ISA instructions, some OS specific instructions. Vitrual memory is added at this level. 4-Assembly level - Lowest "codable" level, generally lowest level software writers use. Only really used when optimazation is needed. 5- High level language- Java, C++, etc. Powerful languages,compliled(translated) into assembly language in order to be executed. 3. CISC - Complex instuction set computer. RISC - Reduced instruction set computer. These two represent two different approaches for designing a processor. A CISC implementation will have many instructions, each which does one little thing. Where as a RISC implementation has much fewer instructions but each one is much more powerfull. Another aspect to note is the the RISC design has many more registers the the CISC design. 4. 1- Mechanical - Late 19th Early 20th century. Lacked power or acuracy to be utilized. 2- Vacum Tubes - Tubes are used to pass signals between components. 32 Bytes takes up a room. 3- Transistors - 1950's. Offer great advantages over Vacum Tubes, faster, smaller and use less heat. 4- Integrated circuts - Many transistors on a single chip. Allows Hundreads of MBytes to be stored in a space the size of a shoe box. 5- VLI- Very Large scale Integration - Lots of integrated circuts, fast! Allows GBytes on a single DIMM. -Moore was one of the founders of Intel. His "law" states that the number of transistor on a chip will double every 18 months, which fits with these models. Kurtzwiel claims that Moore's law won't apply soon because things are in fact getting faster then that. 5. Pipeline architecture is a approach that takes a problem and devides it into steps. There is a stage of the pipeline for each step and data is passed through the pipeline with each stage working on one step of the problem. On a CPU the execute component of the pipeline is usually replicated (super scaled) becuase instructions are often executed multiple times on different data. 6. Attached 7. Attached 8. First the is a call made requesting the datafrom the disk to be sent to memory. Then the disk drive must spin up and read the data (this is where rotational latency(waiting for the disk to spin), seek(finding the right place on the platter) and transfer time come in), it passes the data to the disk controller, which puts it on the bus to be transfered into memory. 9. Double data rate RAM perform one read or write on the rising edge of the fronts side bus, just like typical RAM, however it also performs an action on the falling edge of the clock, allowing twice as many operations per cycle. 10. 1- Provides the next memory address to be read 2- 4-16 decoded, selects which register is to be written to b-bus. 3 - MAR- Memory address register. 4- MDR - Memory Dada Register. 5 - PC - program counter - points to instruction to be executed. 6. MBR 7. TOS - Holds the value of the top of the stack. 8. LV - Local variable pointer. 9. CPP - Constant pool pointer, points to a pool of constants which are referenced with an ofset. 10. 11. OPC 12. H - Input register for the ALU. 13. ALU - Arithmetic Logic Unit- does the math. 14. Shifter - Shifts ALU results if necessary. 15. C-BUS - Provides data for the regiseters to read. 16. ALU control lines. 17. N - Value depends on ALU output. 18 Z - Value depends on ALU output. 19. High-bit - outputs 0 or 1 depending on N,Z,JAMN and JAMZ. 20. 21. Provides where the next instructions is at in the control store. 22. Control Store - stores all the micro code. 23. 25. 26. JAMN/JAMZ 27. ALU and shifter controls. 28. Hold which registers are to read from the c-bus 29. Hold address to be sent to MAR 30. Holds address to be sent 4-16 decoer. 11. Immediate addressing means that the data to be used is comming in the instruction stream, directly after the instruction. Direct addressing means that the data to be used is in the location that is in the instruction stream. Indirect addressing means that the data is stored in the location that the location in the data stream stores. 12. Interupt driven I/O, represents the situation where devices and the CPU have interupt pins. When the device has some input for the CPU or needs output it enables the interupt line. Which is acknoledged by the other device who waits for the data. Programed I/O represents the situation where input and output occur at regular times, therefore they don't have to be accounted for at any given moment. Direct Memory Access. With this approach memory is directly accesed by the devices. 13. The ISA level is just in between the Operating System level and the microarch level. It has some instructions from each of it's neighboring levels, however most of its instructions are just combinations of mircode levels. Virtual memory is added to this level to make the OS level. 14. Virtual Memory is a concept used to give people access to all their information. Basically it lets users address disk space as memory because when the info is actually needed it is placed in memory. There are two main ideas demand paging or the working set approach. With demand paging the needed pages are brought into memory when there is a call for it and a page-fault. The oter approach is the working set aproach in which certian pages are brought into memory along with the called page becuase the will most likely be used. Page replacement algorithims like FIFO or MRU (most recently used) are often used to decide which pages are to be removed to make room for the new ones.