Clock delay

Splits the clock cycle into 4 equal, non-overlapping subcycles. The main clock cycles at 200 time units (Logic Sim measurement). The non-inverting buffers are each set to wait 50 time units before outputting its input. The buffers are linked in a chain--the buffer corresponding to CK4 linked to the output of CK3, CK3 linked to CK2, CK2 linked to the clock. To prevent the subcycles from overlapping, the subcycles are only asserted until the following subcycle is asserted (a delay of 50 time units). CK1(output)=CK1(buffer) & notCK2(buffer).